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7-12
Delay-Locked Loop
Figure 7-4: DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry in Stratix V GX, GS, and GT Devices
SV51008
2014.01.10
DQS/CQ
CQn
DQS/CQ
CQn
DLL
Pin
Pin
Pin
Pin
DLL
Reference
Reference
Clock
DQS Logic
Blocks
Clock
DQS
Phase-Shift
Δt
Δt
Δt
Δt
DQS
Phase-Shift
Circuitry
DQS
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
Circuitry
DQS
Phase-Shift
Circuitry
Phase-Shift
Circuitry
DLL
Reference
Δt
Δt
Δt
Δt
DLL
Reference
Clock
CQn
Pin
DQS/CQ
Pin
CQn
Pin
DQS/CQ
Pin
Clock
The DQS phase-shift circuitry is connected to the DQS logic blocks that control each DQS/CQ or CQn pin.
DQS logic blocks allow the DQS delay settings to be updated concurrently at every DQS/CQ or CQn pin.
Delay-Locked Loop
The DQS phase-shift circuitry uses a delay-locked loop (DLL) to dynamically control the clock delay required
by the DQS/CQ and CQn pin.
The DLL uses a frequency reference to dynamically generate control signals for the delay chains in each of
the DQS/CQ and CQn pins, allowing the delay to compensate for process, voltage, and temperature (PVT)
variations. The DQS delay settings are gray-coded to reduce jitter if the DLL updates the settings.
There are a maximum of four DLLs, located in each corner of the Stratix V devices. You can clock each DLL
using different frequencies. Each DLL can have two outputs with different phase offsets, which allows one
Stratix V device to have eight different DLL phase shift settings.
You can have two different interfaces with the same frequency sharing a DLL, where the DLL controls the
DQS delay settings for both interfaces.
Each I/O bank is accessible by two DLLs, giving more flexibility to create multiple frequencies and multiple-
type interfaces. Each bank can use settings from one or both adjacent DLLs. For example, DQS1T can get its
phase-shift settings from DLL_TR , while DQS2T can get its phase-shift settings from DLL_TL .
Altera Corporation
External Memory Interfaces in Stratix V Devices
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